Biometric matching applications (finger print, palm print, retina, and facial) are ideal candidates for DRC’s FPGA-based AcceliumTM accelerators. Using the massive parallelism of the accelerators results in orders of magnitude1 wall-clock application speed-up vs. the same algorithms executed in software on conventional processors.
Biometric identification is a rapidly growing segment and one that places extraordinary resource demands on the host system.
Fingerprint, palm print, retina, facial, and voice recognition algorithms are concurrently computationally and data intensive applications.
Frequently the resource demand by these systems quickly outstrips even the capacity of the largest monolithic systems forcing use of clusters having in-creased programming and support complexity combined with significantly greater infrastructure needs.
Most biometric identity applications follow the 80/20 rule for wall-clock performance; 80% of the total time-to-solution is consumed
by 20%, or less, of the run-time code. By moving the processing of the critical 20% to the DRC Accelium engine not only is orders of
magnitude speed-up of the critical algorithms achieved but main thread speed-up is also realized.
DRC is partnered with AFIX Technologies, Inc, an international leader in biometric identification systems. The combined approach has resulted in 20X acceleration of subject to database matching with 40X acceleration on the horizon.
Single Engine or Appliance
The DRC Biometrics system is configured into an Accelium accelerator (a PCIe plug-in board) for integration into your application server or storage system. Also available as an in-line appliance; a plurality of accelerators (four or more, depending on the specified chassis) may be installed making the system easily scalable to match your requirements for both economy and throughput.
Installing the DRC Biometrics engine in the system that stores your reference data ensures that analysis is per-formed as closely as possible to the data source for maximum performance and minimized communications latency.
Installing the DRC GraphFind engine in the system that generates or stores graph data ensures that graph analysis is performed as closely as possible to the data source for maximum performance and minimized communications latency.
The Hardware is the Algorithm
The image matching algorithms are instanced as FPGA logic blocks—it is hardware, not software. Unlike conventional computer programs, the FPGA allows
creation of a “custom” processor that is optimized for a single algorithm. Sequential operations are instanced in a “pipeline” such that new data is
accepted and results are generated on every clock cycle once the pipeline is full. Additional performance comes from putting pipelines in parallel.
While a microprocessor does one operation every clock (at best) the FPGA does thousands.
This massively parallel approach to application-specific computing is what gives the DRC Accelium its very attractive SWaP (Size, Weight, and Power) profile compared to conventional systems.
The DRC Biometrics system is easily integrated into your application using a simple, robust, and flexible API callable from any language supporting the use of Linux shared object libraries.
Scalability and Workflow
The system is scalable from one to any number of Accelium accelerators depending on your performance needs. The API is thread and MPI friendly simplifying reliable integration into both Linux and Windows HPC environments—this makes the system compatible with most the workflow/process management and submission engines commonly used in contemporary data centers.